Edit Event: ManyMORE 2008

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<pre> ================================================================================================ === ManyMORE 2008 === Emerging MANY-core architectures in data Mining and infOrmation REtrieval. === http://manymore08.isti.cnr.it === === Colocated with InfoScale 2008 [http://www.infoscale.org] - June 6, 2008 Vico Equense, Italy ================================================================================================ At this workshop, we strive to explore the ever-obfuscating landscape of commodity processor hardware. As processor manufacturers race toward commodity systems employing hundreds of cores, researchers are working out methods and techniques to leverage them. Both AMD and Intel have relatively straight-forward quad core processors which can execute SMP algorithms previously written for SMP systems. On the other end of the spectrum, new GPUs have designs which offer vastly increased floating point throughput at the expense of a complex and somewhat restrictive data path. In the middle lies the Cell BDEA, a nine core streaming processor. Not only do these new architectures advance the parallel programming paradigm, but they also make it mandatory to consider novel approaches in the design of such parallel algorithms. Several natural questions arise. Are extant parallel shared memory algorithms in the IR field positioned to leverage such technologies? Can a streaming, general-purpose processor offer improvements that are not achievable with standard CMPs? What is the impact of software cache management in presence of complex cache hierarchies? Do information retrieval algorithms saturate available off-chip bandwidth? Is there a general-purpose framework which can offer benefits for software memory caches, such as that present in the Cell processor, to reduce average latencies when compared to hardware managed cache? The goal of this half-day workshop is to offer a venue for researchers to explore the challenge of developing data mining and information retrieval algorithms for emerging commodity parallel hardware. The workshop is open to algorithms, systems, parallel programming tools, software cache managements, and parallel frameworks which attempt to leverage these technologies to execute algorithms for classification, clustering, graph analyses, and other data mining and informataion retrieval tasks. Topics of Interest Authors are invited to submit papers concerning the following topics: * Data mining / information retrieval algorithms for emerging processors * Relevent DM/IR performance studies regarding emerging processors, such as: o Scalability o Bandwidth issues o FP throughput o Comparisons with existing SMPs o Explicit vs Hardware managed caching o Tradeoffs between SMT contexts and CMP cores * Middlewares for parallel programming on emerging processors * Middlewares for automating software cache management * Compiler improvements for emerging parallel processors * Data visualization using emerging parallel processors * New metrics for cross-platform evaluations == Chairs Greg Buehrer, buehrer *at* microsoft.com, Microsoft Live Labs Claudio Lucchese, claudio.lucchese *at* isti.cnr.it, ISTI - CNR Pisa, Italy == Program Committee The technical program committee is listed below. * Gagan Agrawal Ohio State, USA * Roi Blanco University A Coruna * Kumar Chellapilla Microsoft Live Labs, USA * Yen-Kuang Chen Inetl Research, USA * Massimo Coppola ISTI-CNR Pisa, Italy * Amol Ghoting IBM Research, USA * Keith Marsolo Cincinnati Children's Hospital - Biomedical Informatics Research, USA * Anthony Nguyen Intel Research, USA * Raffaele Perego ISTI-CNR Pisa, Italy * Sidd Puri Microsoft Live Labs, USA * Fabrizio Silvestri ISTI-CNR Pisa, Italy Others will be announced shortly. == Submission Guidelines We ask that the authors send original, unpublished content. Works in progress are not discouraged. We are using the same format as InfoScale, with a limit of 6 pages. Please refer to their guidelines for further details (http://www.infoscale.org/authorskiticst.shtml). Paper have to be sent by email to both the workshop chairs. Papers will be published with the InfoScale 2008 Conference proceedings, and they will be indexed by the ACM digital library and DBLP. == Important Dates * 11 April 2008 : Intent to Submit (optional, by email to Chairs) * 17 April 2008 : Paper Submission Deadline * 1 May 2008 : Notification of Acceptance * 5 May 2008 : Camera-Ready copies of accepted papers </pre>This CfP was obtained from [http://www.wikicfp.com/cfp/servlet/event.showcfp?eventid=2797&amp;copyownerid=320 WikiCFP]

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